1. Field of the Invention
The invention relates in general to computer-based systems for automatically implementing post-silicon engineering change orders (ECOs) by altering IC layout designs through ECO re-synthesis, optimization and routing.
2. Description of Related Art
Referring to FIG. 1, an IC designer typically generates an initial digital integrated circuit (IC) design in the form of a “register transfer level” (RTL) netlist 10 referencing the conductive networks (“nets”) conveying signals to and from the IC's registers and other clocked devices and using hardware description language (HDL) statements to describe logical relationships between those signals. The designer then uses a computer-based synthesis tool 12 to automatically convert RTL netlist 10 into a “gate level” netlist 14 describing the IC as being formed by interconnected instances of standard cells having known internal layouts, such as logic gates, registers, memories, and other devices for implementing the logic described by the RTL netlist. The designer next employs a computer-based placement tool (“placer”) 16 to convert the gate level netlist 14 into a “placed” netlist 18 indicating the orientation and position of each cell instance within the IC. Placed netlist 18 also references all of the nets that are to interconnect cell instances and indicates which cell instance terminals are connected to each net, but it does not indicate how the nets are to be routed within the IC. A computer-based routing tool (“router”) 20 then converts placed netlist 18 into an IC layout 22, a data file indicating the internal layout, orientation and position of each cell instance and the layout of conductors forming the nets that are to interconnect terminals of those the cell instances. Layout 22 acts as a guide for IC fabrication.
A typical IC consists of many semiconductor, insulating and metallic layers, each formed during IC fabrication in a pattern determined by a separate photolithographic mask. An IC fabricator creates a separate mask for each of the semiconductor, insulating and metal layers based on IC layout 22. An IC's uppermost metallic layers normally form the conductive horizontal segments (“wires”) of the nets that interconnect terminals of cell instances implemented in lower layers of the IC. Conductive vias, extending vertically through insulating layers between the metallic layers, interconnect wire segments formed on the various metallic layers.
After the fabricator produces prototype IC's in accordance with IC layout 22, the IC designer may decide to alter the IC design, for example to resolve timing, testability or yield problems discovered during testing of the prototype IC or to add new functions to a previously fabricated IC. To change the IC design, the designer could repeat the entire design process by generating a new RTL netlist 24, using a synthesis tool 26 to create a new gate level netlist 28, a placer 30 to create a new placed netlist 32, and a router 34 to produce a new IC Layout 36 for guiding fabrication of the revised IC. Since the process of converting new RTL netlist 24 into new IC Layout 36 is essentially automatic, it is possible that the mask for every layer of the IC based on new IC Layout 36 will differ from the mask for the corresponding layer of the IC based on old IC layout 22 even when the differences between RTL netlists 10 and 24 are small. Since masks are expensive, the need to redo the mask for every layer of the IC adds substantially to the expense of the re-design process.
The post-silicon engineering change order (“PSECO”) system was developed to avoid having to redo the mask for every layer of an IC when only relatively small changes are needed to the original IC design following IC fabrication. During the initial design process, a variety of “spare” cell instances of various types are incorporated into gate level netlist 14 to fill space within the IC that would otherwise be unused. The spare cell instances are distributed throughout the IC and are “spare” in the sense that they not connected to any nets and therefore have no effect of IC behavior. Should a designer decide to modify IC logic in some way after masks for the IC have been fabricated, it may be possible to do so by changing only one or more of the metal layers forming the nets interconnecting cell instances so that the fabricator can reuse the existing masks for all other layers when fabricating the revised IC. For example, if a logic block within an IC initially included a small NOR gate and the designer determines after testing the prototype IC's that the NOR gate has insufficient driving power, the designer can modify the layout of the metal layers to reroute the nets to replace the small NOR gate with a larger, more powerful spare NOR gate. Similarly, a designer may be able to alter the logic implemented by a subcircuit within the IC without moving or changing any cell instances by re-routing nets to disconnect some active cell instances from the circuit and to incorporate spare cell instances into the circuit. Thus the change order affects only the masks for the metal layers implementing the nets
Referring again to FIG. 1, to carry out a conventional PSECO operation, the designer generates a new RTL netlist 24 and then manually edits the original placed netlist 18 (step 38) thereby to produce an edited placed netlist 39 that revises the interconnections between cell instances to reflect the changes made to new RTL netlist 24. The changes to RTL netlist 24 involve appropriately interconnecting selected spare cell instances to existing cell instances and removing next interconnecting any existing cell instances that are no longer needed so that they now become spare cell instances. The designer then employs a conventional automated placement and routing tool (router) 40 operating in an “engineering change order” (ECO) mode to convert the edited placed netlist 39 to an ECO IC layout 42. In the ECO mode, router 40 is restricted to re-routing nets by modifying only the IC's metal layers. In some systems router 40, rather than the designer, will select the spare cell instances to be used. Since ECO layout 42 differs from the original IC layout 22 only with respect to the metal layers, the IC fabricator need create new masks only for the IC's metal layers. The ECO approach thus saves cost of re-fabricating masks for other IC layers.
Since the designer may erroneously change circuit logic when manually performing the netlist-editing step 38, the designer may also initiate the entire synthesis, placement and routing process (26, 30, 34) to produce a new IC layout 36. Since that process is not subject to logic errors, IC layout 36 will define an IC layout that will not have such errors. The designer can then employ a computer-based equivalence checker 44 to compare ECO IC layout 42 to new IC layout 36 to determine whether the ICs they describe are logically equivalent. If the ECO IC layout 42 is equivalent to IC layout 36, the designer will know ECO IC layout 42 has no logic errors and can be used as a guide for fabricating the masks for the metal layers of the revised IC.
Although the PSECO approach to modifying an IC design (also known as the “metal-only ECO” or “spare-cell instance-aware ECO” approach) saves money by allowing the fabricator to reuse masks for most layers, it does so at the cost of the engineering effort needed to manually edit the gate level netlist at step 38, a tedious, time-consuming and error-prone process. Since designers normally think of an IC design at the abstract level of the RTL netlist 10, designers find it hard to decipher and correctly modify a placed, gate level netlist 18 to change the logic it implements and to select the spare cell instances that are best positioned to enable router 40 to satisfy all routing, timing and other constraints. When router 40 fails to successfully generate a suitable ECO IC layout 42, the designer must re-edit netlist 39 to choose different spare cell instances and then allow router 40 again try to generate a suitable ECO IC layout 42. The edit/router steps 38 and 40 of the PESCO process may iterate several times in order to arrive at a suitable ECO IC layout 42, and may never converge to an acceptable layout solution. Since the PSECO approach is likely to fail when the scale of change is large, IC design companies typically use PSECO only for small-scale changes.
NTU paper “ICCAD 2007. 7C.1 ECO Timing Optimization Using Spare Cell instances and Technology Remapping” Yen-Bin Chen, Jia-Wei Fang, Yao-Wen Chang—National Taiwan Univ., Taipei, Taiwan (published Nov. 5, 2007), focuses on ECO optimization for fixing timing issues. Chen et al teach to solve timing issues based on spare cell instance locations by attempting to remap similar spare cell instances to different locations to improve timing. Chen et al teach to perform re-synthesis for any path that fails to meet the timing requirement. “Re-synthesis” refers to remapping cell instances on the timing path to different types of spare cell instances that yield the same Boolean function values but may improve the overall timing. Chen et al limit re-synthesis to a single path.
National Tsing Hua University paper. Y. M. Kuo, Y. T. Chang, S. C. Chang, and M. Marek-Sadowska, “Engineering Change Using Spare Cell instances with Constant Insertion” (published Nov. 11, 2007) focuses on PSECO re-synthesis with constant insertion by considering routing distances but not timing information when performing PSECO synthesis.
U.S. patent application Ser. No. 11/564,422, publication number 2007/0124712 A1, filed Nov. 29, 2006 teaches a method for fixing timing problems in an IC, but not within a post-silicon ECO environment.